|
To overcome the "ripple
through" effects of
asynchronous counters,
synchronous types are
used.
All the flip-flops are
clocked simultaneously,
and change state at the
same time.
Bear in mind, that when
J and K are both low, a
flip-flop will not
change state, upon the
arrival of a clock
pulse.
When J and K are both
high, then Q will toggle
upon the arrival of a
clock pulse.
The two AND gates are
decoders, which
recognise the state of
the A, B and C outputs.
J and K of flip-flop 1
are tied high and it
will always toggle on a
clock pulse.
Flip-flop 3 cannot
change state unless AND
1 output is high (A and
B high).
Flip-flop 4 cannot
change state unless A, B
and C are all high,
making the output of AND
2 high.
At the start, all
outputs can be set to
zero by means of the
CLEAR line.
On the first clock
pulse, A goes high,
since J and K of
flip-flop 1 are both
tied high.
The first and second
flip-flops are now set
to toggle on the next
clock pulse.
On the second clock
pulse, any flip-flops
with J and K high will
toggle.
So A goes low and B goes
high.
On the third clock
pulse, A goes high and B
stays high.
This means that J and K
of flip-flop 3 are high.
On the fourth clock
pulse, A and B go low
and C goes high.
Flip-flop 4 can only
toggle when A, B and C
are all high.
This will be on the
eighth clock pulse, when
D goes high and A, B and
C go low.
|
