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To ensure that
flip-flops change in
synchronism with other
parts of the circuit,
they are not allowed to
change state until they
receive a CLOCK PULSE.
SET and RESET cannot
affect the outputs
unless the clock pulse
is high.
In the TIMING DIAGRAM
below, at A, SET is
HIGH but the CLOCK is
LOW, so there is no
change in the outputs.
At B, SET is still HIGH,
and CLOCK is HIGH.
Therefore Q goes HIGH.
At C, the CLOCK is HIGH
and RESET has gone HIGH.
Therefore Q goes LOW.
At D, the CLOCK is HIGH
but SET is LOW.
There is no change in
output levels.
At E, CLOCK and SET are
both HIGH.
Q goes HIGH.
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